1. Technical Field
One or more embodiments of the invention relate generally to the field of computer systems. More particularly, certain embodiments relate to power delivery in a computer system.
2. Background Art
Energy efficient performance is an increasingly important requirement for many computing applications. In servers and other computer platforms, operation of input/output (I/O) interface hardware is a significant contributor to overall power consumption. Performance analysis for various computer platforms has shown that the bandwidth of I/O links can be generally quite low even when such computer platforms are operating near peak system power load. Even when no transaction is processed over an I/O link of a platform, associated I/O interface resources consume close to their peak power. Power wastage during such low bandwidth utilization periods results in poor energy efficiency.
Power consumption by such I/O hardware has traditionally been reduced by scaling link speed and/or link width. Some link power reduction schemes use dynamic link width modulation (DLW), which adjusts link width dynamically based on bandwidth requirements, and gates a clock otherwise used to operate the currently inactive hardware for the link. Current I/O link power management (LPM) policies such as L0s, L0p, L1 rely on clock gating. However, as successive generations of computer systems continue to scale in terms of size and speed, the performance of such computer systems are increasingly sensitive to incremental improvements in energy efficiency.